1. Technical Field
The present invention relates generally to electrical circuits and in particular to serial link receivers.
2. Description of the Related Art
High speed serial (HSS) link receivers are key components in data receiving circuits commonly utilized on/connected to on the receiving end of an electrical data transmission line. These HSS receiver, as they are frequently called, are required to accommodate a wide range of termination voltages, from 0V up to a potential exceeding the chip VDD.
Additionally, the HSS link receiver is also required to provide certain other power characteristics for proper operation. Among these power characteristics are: (1) The HSS receiver should tolerate these wide ranges of termination voltages when the receiver is partially powered; (2) The HSS receiver should interoperate with other receiver components powered by the chip's VDD; and (3) Power consumption of the HSS receiver should be minimized.
Other functional requirements of the receiver include: (1) The HSS receiver should present a high impedance when required; (2) The HSS receiver should function similarly over all signaling rates and transition densities; (3) The HSS receiver should reject common mode noise; and (4) The HSS receiver should operate at an optimal common mode voltage. Finally, a specific design characteristics desired of the HSS receiver is that the area of the HSS receiver should be minimized.
As described below, various receiver input networks provide partial solutions that address a few of the problems/requirements stated above; However, none of these networks address all of the problems in one solution. One conventionally implemented solution, which purports to accommodate these varying requirements for an HSS receiver, is illustrated by FIG. 1. As shown, the HSS receiver 100 comprises a pair of series-connected capacitors 114A and 114B respectively coupling the receiver's input signals 201 and 203 to the preamplifier 113. However, this solution does not function well with low signaling rates or for arbitrarily long data run lengths. Additionally, this solution occasionally requires prohibitively large amounts of area to accommodate the large capacitors.
An alternative solution powers the input network and potentially part of the receiver from the termination voltage. This solution requires much more power be supplied because all current is now drawn from a much higher voltage supply. Potentially, however, this alternative solution does not address the need to handle lower termination voltages. Also, this solution may typically have limited bandwidth. In addition, power sequencing or latchup problems may result from powering the receiver from two supplies.
Yet another alternative solution utilizes a high common mode input network in parallel with a low common mode one. The outputs of these two networks are then multiplexed together, and the final output is then sent to the receiver input. This solution requires a large amount of power in the low common mode input network and in the multiplexing stage in order to provide the necessary bandwidth. In addition, this solution potentially doubles the parasitic load seen at the input of the network and decreases the return loss margin.